Image sensors traditionally are made up of an array of light sensitive pixels. The image sensor read-out the value of each pixel to produce an image. Before the array of pixels is exposed to receive light, each pixel is reset. As shown in prior art FIG. 1, a current column source ICOL is provided for each column to bias the pixels PIX of that column and, as such, reset their values.
Each column current source ICOL is one half of a current mirror circuit. A diode-connected transistor MPIAS makes up the other half of the current mirror and is common to each column current source ICOL. The current ICOLBIAS is mirrored at ICOL<1> to ICOL<col>. The current column source ICOL is not required continuously during an imaging cycle, but only when the pixel values are to be reset for integration and readout.
Consequently, to reduce power consumption the circuit comprises two reference currents in parallel 11 and 12. A switch SW is provided for selectively connecting the reference current 12. When the current sources are required the switch is closed and ICOLBIAS is equal to the sum of the two reference currents 11, 12. When the current sources are not required, the switch SW is opened and ICOLBIAS is equal to the reference current 11.
When switching between values of ICOLBIAS there is an inherent lag associated with powering up and down of the array due to the associated parasitic capacitance of the array. It may take 5 ms or longer to switch between values of ICOLBIAS. As pixel arrays get larger the parasitic capacitance increases, and the time to switch between values of ICOLBIAS increases further.
As such, as shown in prior art FIG. 2, which relates to European Patent Application 4,252,834, a single current source is used in combination with a resistive load to provide two levels of reference current depending on whether the resistive load is short-circuited or not. In FIG. 2 a plurality of column current sources 10 are shown. Each column current source 10 has common elements being a diode-connected transistor MBIAS and reference current source ICOLBIAS thereby forming a current mirror. A series of resistors MRESLOAD are connected between each current column source 10 and the transistor MBIAS. A switch 13 is connected across the series of resistors MRESLOAD enabling a short across the series of resistors MRESLOAD.
When the column current sources 10 are required the switch 13 is turned on shorting the series of resistors MRESLOAD and allowing the currents ICOL<1> to ICOL<4> to mirror ICOLBIAS. When the column current sources 10 are not required the switch 13 is turned off. The series of resistors MRESLOAD now have a potential difference across them which reduces the gate-source voltage of the transistor MBIAS. As the column current sources 10 and transistor MBIAS form a current mirror, the column current sources 10 mirror the gate-source voltage of MBIAS and therefore the currents ICOL<1> to ICOL<4> are reduced accordingly.
With both of the above arrangements the column current sources are either at a low value or a high value depending on whether the pixel and associated circuitry is in operation or not. In fact, for a 4T pixel, a high value of current is only typically required when the transfer gate transistor has been switched on. At other times, it would be possible to use a medium value current level, which would result in less current being consumed during pixel readout.